1. Field of the Invention
The present invention relates to a multilayer interconnection structure of a semiconductor device in which different interconnection layers of multilayer interconnection are connected at predetermined positions, and a method for forming the multilayer interconnection structure. In particular, the present invention relates to a multilayer interconnection structure of a semiconductor device, the multilayer interconnection structure including a connecting interconnection for connecting predetermined two points of different interconnection layers of multilayer interconnection structure with a short distance therebetween.
2. Description of the Related Art
In a conventional LSI, multilayer interconnection is formed using an algorithm for lattice interconnection. Also, through holes are formed in a lattice pattern in an interlayer insulating film to extend to lower interconnection perpendicularly to a semiconductor surface so that different interconnection layers of multilayer interconnection are connected with conductive interconnections formed in the through holes.
However, the above-described multilayer interconnection has the limitation that it is formed in a lattice pattern. Therefore, when a predetermined point is connected to a point diagonal to the predetermined point, additional interconnection is required. Namely, when the two points of interconnection layers in the same plane are connected, the required interconnection length is √{square root over (2)} times or more as long as the slant distance between two points, while when the two points of different interconnection layers are connected, the required interconnection length is √{square root over (3)} times or more. As a result, the interconnection resistance and interconnection capacity are increased to cause a signal delay.
FIG. 16 shows a multilayer interconnection technology as Conventional Example 1 in which increases in interconnection resistance and interconnection capacity are suppressed using a lower interconnection layer with a interconnection distance λ in the same plane, which belongs to a first interconnection lattice layer 158 or a second interconnection lattice layer 157, and an upper interconnection layer of diagonal interconnection with a interconnection distance √{square root over (2)}λ in the same plane, which belongs to a third interconnection lattice layer 155 or a fourth interconnection lattice layer 156 (Japanese Unexamined Patent Application Publication Nos. 5-102305 and 2000-82743). Namely, different interconnections belonging to the first or second interconnection lattice layer are connected using the third or fourth interconnection lattice layer. Also, through holes are formed in an interlayer insulating film in a lattice pattern comprising the intersections of interconnection in the first (or second) interconnection lattice layer and interconnection in the third (or fourth) interconnection lattice layer in such a manner that the through holes extend to interconnection belonging to the first (or second) interconnection lattice layer in the direction perpendicular to a semiconductor surface. Then, interconnection belonging to the first (or second) interconnection lattice layer is connected to interconnection belonging to the third (or fourth) interconnection lattice layer by using the conductive interconnections formed in the through holes. In the configuration of Conventional Example 1, the length of interconnection in a plane for connecting different interconnections belonging to the first interconnection lattice layer using interconnection belonging to the third interconnection lattice layer is 1/√{square root over (2)} of that using interconnection belonging to the second interconnection lattice layer.
In a technique of Conventional Example 2 proposed as a technique for forming through holes in an interlayer insulating film so that the through holes reach lower interconnection, the through holes are formed using a FIB (focused ion beam) apparatus, for obliquely observing a predetermined point on the lower interconnection from a point in a plane different from the plane of the lower interconnection (Japanese Unexamined Patent Application Publication Nos. 06-112194 and 2-2260790).
In a technique of Conventional Example 3, through holes are formed at two points or more using a FIB apparatus so as to vertically reach lower interconnection, and then interconnection is formed by a laser CVD method, for connecting the two points together (Japanese Unexamined Patent Application Publication No. 62-229956). Namely, connecting interconnection not requiring lattice interconnection is used as interconnection for connecting the two points in the same plane.
The FIB apparatus is used for processing a submicron region by applying an ion beam converged by an electrostatic lens to an object to be processed. The laser CVD method comprises applying FIB (including a laser beam) to a predetermined portion of an object placed in a metal organic compound gas to deposit a metal material only on the FIB-irradiated portion of the object using the metal organic compound gas.
In a conventional multilayer interconnection structure, in order to connect upper interconnection and lower interconnection, an additional lower interconnection extending from an intersection point between the lower interconnection and the upper interconnection is required for connecting the upper interconnection to the lower interconnection. Next, a through hole and conductive interconnection in the through hole are required, the through hole vertically extending from the intersection point between the lower interconnection and the upper interconnection.
Since the additional lower interconnection is required, arrangement of the lower interconnection layer has no degree of freedom, and thus the interconnection density cannot be increased. Furthermore, the connecting interconnection comprising the additional lower interconnection and the conductive interconnection in the through hole does not necessarily take the shortest route for connecting the upper interconnection layer and the lower interconnection layer.